December 6, 2022
My discrete computer lacks two major things: sound and network. The project I describe here is the first step to making it capable of network communication. I don’t touch the computer itself now, but instead build a transceiver which converts a 10BASE-T Ethernet signal to SPI and back. I use an STM32 MCU to test my transceiver for now. In the future I plan to connect the transceiver to the discrete computer.
Ethernet operation briefly
10BASE-T uses two differential pairs: one for transmission and one for reception. Each pair is coupled through a transformer.
The signal is differential and Manchester-encoded. When idle, a network device must send normal link pulses (NLP): 100 nS positive pulse every 16 mS. These pulses let the other side know that something is connected to the port.
Ethernet data comes in frames. Each frame starts with a fixed synchronization preamble and ends with a frame check sequence (FCS). The synchronization sequence consists of 62 alternating ones and zeroes and finally two ones. Each byte in the frame is transmitted LSB-first.
Receiver
If you look at a Manchester-encoded signal, you can see that the data is already there. The current bit’s value is present on the line right after the mid-bit transition.
To construct an SPI signal from that, it’s enough “just” to generate a clock signal, the low-to-high transitions of which will be used to latch a bit from the original Manchester-encoded line.
Clock generation
When researching for this project, I found this blog post. Its author uses a 75c1168 chip to convert the differential 10BASE-T signal into usual 5V logic levels and then detects edges by XORing delayed signal with itself. I stole this part of the schematics from him:
However, after edge detection Andrew (the author of the mentioned post) casts some complicated PLL magic which is above my level. I decided to take an easier path. Having the base signal and its edges is almost enough for SPI: we could latch the bit using the edge signal. This signal already provides positive transitions in the right spots, but the problem is that sometimes extra pulses come between the ones we want to use as clock:
My idea was to filter the extra edges out by a monostable non-retriggerable circuit. The circuit will trigger on the first edge and produce a pulse of approximately 75 nS. During that time another edge may come, but it will be ignored by the circuit. This new signal can be used as an SPI CLK now.
The monostable edge filter is built around an RC circuit and some invertors.
In an idle state edge is zero, which makes the AND gate U4C output zero. Q2 is closed and R5 pulls U2E input high. This high logic value, twice inverted, goes back to the other input of U4C. When edge goes high, the output of U4C goes up and opens the transistor. The capacitor is quickly discharged, driving U2E’s input low. This propagates back to U4C, switching its output back to low. Q2 closes, C9 starts to charge through R5. During this slow charge time the feedback signal remains low and keeps further edges from propagating through the AND gate.
Frame detection
When the signal on the li
