Rama Puligadda, CTO at Brewer Science, sat down with Semiconductor Engineering to talk about a broad set of changes in semiconductor manufacturing, packaging, and materials, and how that will affect reliability, processes, and equipment across the supply chain.

SE: What role do sacrificial materials play in semiconductor manufacturing, and how is that changing at new process nodes?

Puligadda: We are talking about materials that perform certain functions that enable fabrication processes and are removed subsequently. One of the challenges in

the new nodes is that these films are getting thinner and thinner. We’re in the single-nanometer range for these thin films, where they are expected to continue to be uniform and defect-free. Another important challenge is planarization of a wide range of features without bias, and also filling large or high-aspect ratio gaps. For most of the future nodes, the structures will continue to get taller. Additionally, there is a need to withstand very high processing temperatures.

SE: And quality now is being measured in parts per quadrillion, right?

Puligadda: Exactly. Our materials are expected to not have any defects on the wafer when coated and after they are removed.

SE: Related to that, Brewer Science pointed out several years ago that not everyone in the supply chain is focused on semiconductors, so their goals for purity were not stringent enough. Has that improved?

Puligadda: Yes, but we still have to push our suppliers to meet standards they didn’t even know about before — especially those that predominantly make materials for different industries. They never had to worry about parts per quadrillion. That’s a relatively small number of our suppliers, though. Most are delivering quite well now, and where it’s not possible to find that level of purity, we’re working toward vertical integration so we can make those high-quality monomers and raw materials ourselves.

SE: With regard to planarization materials, what steps are those being used for? Are there sacrificial materials in vias and interconnects?

Puligadda: Not always. But in a lot of cases, they have to do additional processing so they can fabricate structures in other areas of the wafer, or on top of the structure that they’ve already built. This is when they want a material that temporarily fills the gaps or planarizes the structures underneath. That material has to be removed without residue, and as we move to smaller nodes, that is one of the biggest challenges.

SE: How is that done?

Puligadda: It can be wet or dry, depending on the structure. The high-aspect structures can be very delicate and must be protected through the cleaning process, as well, so they can’t use agitation or anything harsh. Any combination of wet or dry is possible.

SE: Are you seeing new issues stemming from advanced packaging?

Puligadda: The newest trend we’re seeing is hybrid bonding. That requires extremely flat, defect-free surfaces in order to bring them together reliably.

SE: Basically, you’re trying to melt the copper evenly, but in the past you could probably perfect this process across a billion-chip run. Now, we’re seeing smaller batches of more customized designs, with the potential for die shifting. Is that as a big a problem as everyone originally thought?

Puligadda: Die shift is a major challenge. It used to be that the whole system was on a chip. Now they’ve broken it down or disaggregated into chiplets. We can put them on top of each other, or side by side, or wherever we need to integrate various functionalities in a package. It’s basically heterogeneous integration. We’re joining one chip on top of the other, or on top of a wafer, and you can’t have any die-shifting at these very small dimensions. We are working in that area, and have a few technologies that make it possible.

SE: Can you give an example?

Puligadda: One approach is to apply an adhesive material on a temporary carrier and populate that carrier with dies. You can either do over-molding or attach other die to it, or attach it to the wafer, and you can do that without having any shift in the dies. We’re able to do whatever that process requires with very minimal shift in the die. But as the die sizes go down, and in certain applications these can be pretty small, then this isn’t the best solution. It works, but it’s not very elegant. So we’re working on more elegant solutions where you could attach the die directly to the wafer, and over time that will reduce the cost for customers.

SE: Does it get harder as more circuitry is added into RDL? Bas